As integrated circuit lithography has advanced to the current state of reduced printing features (e.g., in the 10-20 nm range or smaller), Static Random Access Memory (SRAM) cells have become much smaller. Unfortunately, the concomitant increase in the variability of individual transistor performance has made it increasingly difficult to maintain robust operation of these memory cells across a wide window of process, voltage, and temperature conditions. The advent of three dimensional transistors, often referred to as “finfet” or “frigate” devices, aggravates this difficulty by quantizing the available transistor sizes. Small adjustments in the relative sizing of access, pull-up and pull-down transistors is no longer possible. As a result of these trends, SRAM designs may need to rely on read and write assist circuits to function properly.
Many read and write assist circuit techniques have been previously developed. Read assist circuits are employed to prevent the memory cell from losing its stored value during a read operation. Write assist circuits are employed to ensure that the memory cell correctly stores the value being written to it. However read and write assist circuits have associated costs, in terms of area and power consumption.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.